Various methods for making complementary transistors on SOI substrates are known in the art. Foerstner et al., in U.S. Pat. No. 5,164,326 and Usui et al., in U.S. Pat. No. 5,162,254 teach methods for making complementary bipolar and CMOS transistors on SOI substrates. Eklund and Eklund et al., in U.S. Pat. Nos. 5,049,513 and 5,102,809, respectively, teach a fabrication process for making BICMOS devices on a SOI substrate, while Lee et al., in U.S. Pat. No. 4,910,165 teaches a method for forming epitaxial silicon-on-insulator structures using oxidized porous silicon and discloses use of this epitaxial silicon for MOS, CMOS or bipolar transistors.
To date, the prior art has taught processes for making integrated circuits having bipolar and CMOS transistors on SOI substrates. The ability to make complementary bipolar, complementary MOS and complementary DMOS transistors would enable smart power applications where power devices, control logic and analog functions on a single integrated circuit is desirable. The full complement of complementary devices on a single integrated circuit leads to versatile and simplified circuits.